The present invention relates generally to a wafer level semiconductor package and a method for manufacturing the same.
Recent developments have lead to semiconductor chips with a high integration density of data and fast data processing speed. These semiconductor chips must find a way to prevent the generation of heat caused when the semiconductor chip with the high integration density of data and the fast data processing speed operates, as the heat causes a lowering in the performance of the semiconductor chip. In order to prevent the generation of heat, most recently developed semiconductor chips are required to have a low voltage operation characteristic.
In order to satisfy the low voltage operation characteristic of the semiconductor chip, the semiconductor chip requires a larger number of power supplying pads. However, semiconductor chips have a limited area, making it difficult to form the larger number of power supplying pads. In addition, the size of the semiconductor chip increases when a larger number of power supplying pads is formed in the semiconductor chip.
Additionally, internal wiring of the semiconductor chip is used to provide power to a specific portion of the semiconductor chip, e.g. an edge portion of the semiconductor chip. In this case, a problem occurs, in that sufficient power cannot be provided to the edge portion of the semiconductor chip through the internal wiring of the semiconductor chip.